1. Field of the Invention
The present invention relates to a method of and an apparatus for providing conductive cores in vias in a substrate; more particularly, to a method of filling high aspect ratio vias.
2. Description of the Related Art
A partial listing of conventional techniques for filling vias includes melting, capillary wetting, wedge extrusion, wire insertion, electroless plating, electro-forming, double-sided sputtering and through-hole plating, screen printing and screen printing/stenciling with vacuum pull-through. A discussion of many of these techniques can be found in "Forming Electrical Interconnections Through Semiconductor Wafers," T. R. Anthony, J. Appl. Phys., Vol. 52, No. 8, August 1981. These conventional techniques lack the ability to provide void-free, low resistance conductive cores in high aspect ratio vias. Void-free vias are required to provide the low resistance and reliability required in packages which form the heart of large computing devices.
As used herein, the term "chip(s)" refers to an encapsulated die having bonding pads provided thereon, and the term "package(s)" refers to devices for housing and/or interconnecting plural semiconductor chips.
Two different types of packages have been used to provide connections between the various chips in a package (or interconnect system), so-called "two-dimensional packages" and "three-dimensional packages." In a two-dimensional package individual leads connecting semiconductor chips provided on the exterior of the package pass in the x, y and z directions within the package. Such a package usually comprises a plurality of wafers provided in a stack with x and y interconnects on the surface of or contained in the wafers and z direction interconnections passing through the wafers. The z direction interconnections are usually provided by vias in the wafers.
In a three-dimensional package, semiconductor chips are mounted within the package; semiconductor chips may also be provided on the exterior of the package. Accordingly, a three-dimensional package may incorporate a larger number of semiconductor chips, requiring a larger number of interconnections and greater cooling capabilities. Moreover, the interconnect system becomes more complicated because of the limited areas where x, y and z direction connections can be provided. Again, vias are used to provide the z-axis electrical interconnections. One example of a three-dimensional package is disclosed in co-pending application Ser. No. 154,852, assigned to the assignee of the subject Application, which is hereby incorporated by reference.
To determine the relative capabilities of different packages or interconnect systems several standards are utilized. The most common standard for comparing the relative capabilities of interconnect systems is the number of interconnects per unit volume of package. A similar standard is the number of pins (or leads) per unit volume of package. Other methods of comparison include computing the package volume per chip and the number of gates per unit volume of package.
As the number of interconnects per unit volume increases the density of signal carrying elements must also increase. One such signal carrying element is the vias which transmit electrical signals through substrates, i.e., in the z-axis in a package. The two- and three-dimensional packages currently being designed require increased via densities, reduced via diameters, and, at the same time, reduced via resistivity to increase signal propagation velocities. Increased via densities and reduced via diameters provide more interconnects, but at the same time lead to problems in resistivity and reliability, in particular, reduced via diameters create difficulties in fabricating void-free vias.
The most popular technique for filling vias, particularly those in multilayer printed circuit boards, is screen printing with fine-mesh screens--the age-old technique of silk screening. Certain manufacturers have combined silk screen techniques with the use of a vacuum on the opposite side of the substrate. Silk screening is an unsatisfactory method for filling small-diameter vias because the mesh of the silk screen interferes with proper via filling.
Some manufacturers have created vias using molten metal to melt or burn its way through a substrate while leaving a conductive trail in the substrate. This method is described in the following U.S. Pat. Nos.: 4,398,974; 4,275,400; and 4,239,312.
Another conventional method of via filling involves using a squeegee to force a conductive paste into vias. This method is not useful for high aspect ratio vias where is it necessary to force the paste into a via which has a much greater length than diameter.
Another type of via or through connection and a method of manufacturing same are disclosed in U.S. Pat. Nos. 3,705,332; 3,775,844; and 3,813,773.
All of the conventional via filling methods have one or more severe drawbacks such as:
1. An inability to achieve void-free vias;
2. An inability to fill high aspect ratio vias (via length/via diameter greater than 6);
3. An inability to fill small-diameter vias (diameter less than 150 .mu.m);
4. A lack of compatibility with high via densities (greater than 5000 vias/in.sup.2); and
5. Providing vias with unacceptably large electrical resistance.